A long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield during IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions.
With the scaling down of integrated circuit dimensions, openings, which are etched within the integrated circuit, are reduced in size. The aspect ratio of the opening, which is defined as the ratio of the depth of the opening to the width of the opening, increases with scaling down of integrated circuit dimensions.
The present invention is described with copper metallization for small geometry integrated circuits. However, the present invention may be used with any other conductive material that is amenable for small geometry integrated circuits aside from just the example of copper, as would be apparent to one of ordinary skill in the art from the description herein.
As an integrated circuit is scaled down, metallization, which interconnects devices on the integrated circuit, is also scaled down. Given the concerns of electromigration failure and line resistance with smaller metal lines and vias, copper is considered a more viable metal for smaller metallization dimensions. Copper has lower bulk resistivity and potentially higher electromigration tolerance than aluminum. Both the lower bulk resistivity and the higher electromigration tolerance improve circuit performance.
However, copper lines cannot be etched using conventional etching processes as used for aluminum. Thus, copper lines are typically fabricated using a damascene etch process. In such a process, a trench is etched within an insulating layer. That trench is then filled with copper. The surface of the integrated circuit is then polished such that the copper line is contained within the trench.
Referring to FIG. 1, integrated circuits typically include multi-level metallization. A first metal line 102 is contained within a first trench 104 etched in a first trench insulating layer 106. A second metal line 108 is contained within a second trench 110 etched in a second trench insulating layer 112. The first metal line 102 is on a first metallization level on the integrated circuit, and the second metal line 108 is on a second metallization level on the integrated circuit. A via interconnects the metal lines 102 and 108 on the two different metallization levels. A via plug 114 is comprised of a conductive material and is disposed within a via hole 116 etched in a via insulating layer 118. The insulating layers 106, 112, and 118 are comprised of any insulating material such as any form of oxides as is known to one of ordinary skill in the art.
Referring to FIG. 2, if the second trench 110 and the via hole 116 were not filled with a conductive material, a top view of the integrated circuit of FIG. 1 shows the second trench 110 running over the via hole 116. The first metal line 102 is disposed on the bottom of the via hole 116. FIG. 1 is a cross-sectional view of the integrated circuit of FIG. 2 along line AA after the via hole 116 and the second trench 110 have been filled with a conductive material.
A dual damascene etch refers to an etching process whereby a via hole and a trench are etched away with one etching step or a series of etching steps. Referring to FIG. 3A (which shows a cross-section along line AA of the integrated circuit of FIG. 2), a dual damascene etch process includes a step of depositing a bottom nitride layer 302 adjacent a first metal layer 304. A via insulating layer 306 is deposited adjacent the bottom nitride layer 302.
A via masking layer 308 is deposited adjacent the via insulating layer 306. The via masking layer 308 is etched to have a via pattern for defining a via hole in the via insulating layer 306. The via masking layer typically is comprised of a hard mask material such as nitride or any other type of dielectric material which is known to one of ordinary skill in the art to be an etch-stop material.
In addition, the via masking layer is disposed with respect to the first metal layer 304 such that the first metal layer 304 is exposed at the bottom wall of a via hole 316. In this manner, a first conductive material filled within the via hole 316 forms a conductive path with the first metal layer 304.
A trench insulating layer 310 is deposited adjacent the via masking layer 308. Then, a photoresist layer 312 is deposited adjacent the trench insulating layer 310. The photoresist layer 312 is further processed to have a trench pattern for defining a trench in the trench insulating layer 310. The via pattern in the via masking layer 308 and the trench pattern in the photoresist layer 312 are aligned such that the trench and the via hole form a contiguous opening. In this manner, the first conductive material filled within the via hole forms a conductive path with a second conductive material filled within the trench, as illustrated in FIGS. 1 and 2.
Referring to FIG. 3B, a trench 314 is etched out of the trench insulating layer 310 with the photoresist layer 312 defining the size, shape, and location of the trench 314. Furthermore, in a dual damascene etch process, the via hole 316 is also etched out of the via insulating layer 306. Referring to FIG. 3A, the trench insulating layer 310 abuts the via insulating layer 306. Thus, using a dual damascene etch process, the trench 314 and the via hole 316 are etched with one etching step, and the trench 314 and the via hole 316 are contiguous openings.
Referring to FIG. 3C, any part of the masking layers 308 and 312 (and the nitride layer 302) that are exposed are etched away. Then, the via hole 316 and the trench 314 are filled with conductive material. The conductive material in the via hole 316 forms a conductive path between the first metal layer 304 and the conductive material in the trench 314.
Referring to FIGS. 3C and 4, the dual damascene opening is comprised of the via hole 316 and the trench 314 that are contiguous openings. The first metal layer 304 is exposed at the bottom wall of the via hole 316. Referring to FIG. 4, the first metal layer 304 may be coupled via a tungsten plug 402 to an active area of an integrated circuit.
Referring to FIG. 4, in the prior art method for filling the dual damascene opening, a seed layer 404 of copper is deposited into the via hole 316 and the trench 314. Then the via hole 316 and the trench 314 are filled with copper by electroplating deposition of copper from the seed layer 404. In such a process, a voltage bias is applied on the wafer having the dual damascene structure of FIG. 4 such that a reduction of copper ions results in deposition of copper onto the wafer, as known to one of ordinary skill in the art.
Referring to FIG. 4, as geometries of integrated circuit structures are scaled down, the aspect ratio of the trench 314 and especially of the via hole 316 increases as the width of the openings are scaled down. Thus, conformal deposition of the seed layer 404 into the corners of the via hole 316 is more difficult to achieve. As illustrated in FIG. 4, the seed layer 404 may not reach the corners of the via hole 316, and in that case, the copper plug within the via hole 316 does not make good contact with the first metal layer 304. Such poor contact of the via plug with the first metal layer 304 results in a high rate of electromigration failure of the via plug within the via hole 316 and thus in degradation of integrated circuit performance. With some high aspect ratio via holes, such poor contact may result in complete electromigration failure of the integrated circuit.
In addition, during electroplating of copper from the seed layer 404, copper is deposited from the seed layer on the side walls of the via hole 316 as illustrated in FIG. 4. With the high aspect ratio via hole 316, as copper is deposited from the side walls toward the top of the via hole 316, the via hole 316 may close off with copper deposition from the side walls toward the top of the via hole 316. In that case, a void 406 which is an opening within the via plug or a plurality of such voids may form within the via plug. Such voids result in higher electromigration failure of the via plug and thus in degradation of integrated circuit performance. With some high aspect ratio via holes, such voids may lead to complete electromigration failure of the integrated circuit.
Thus, a method for compactly filling dual damascene openings having high aspect ratio is desired such that electromigration failure within small geometry integrated circuits is minimized.